Semi-conductor components, e.g. corresponding integrated (analog and/or digital) computer circuits, semi-conductor memory components such as functional memory components (PLAs, PALs, etc.) and table memory components (e.g. ROMs or RAMs, particularly SRAMs and DRAMs) etc. are subjected to numerous tests during the course of the manufacturing process.
For the simultaneous manufacture of a plurality of (generally identical) semi-conductor components, a so-called wafer (i.e. a thin disk consisting of monocrystalline silicon) is used. The wafer is appropriately processed (e.g. subjected to numerous coating, exposure, etching, diffusion and implantation process steps, etc.), and subsequently sawn up (or e.g. scored and snapped off), so that the individual components become available.
During the manufacture of semi-conductor components (e.g. DRAMs (Dynamic Random Access Memories and/or dynamic Read/Write memories), particularly of DDR-DRAMs (Double data Rate—DRAMs and/or DRAMs with double data rate)) the components (still on the wafer and incomplete) may be subjected to appropriate test procedures at one or several test stations by means of one or several test apparatuses (e.g. so-called kerf measurements at the scoring grid) even before all the required above processing steps have been performed on the wafer (i.e. even while the semi-conductor components are still semi-complete).
After the semi-conductor components have been completed (i.e. after all the above wafer processing steps have been performed) the semi-conductor components are subjected to further test procedures at one or several (further) test stations; for instance the components—still present on the wafer and completed—may be tested with the help of corresponding (further) test apparatuses (“disk tests”).
In corresponding fashion one or more further tests may be performed (at further corresponding test stations and by using corresponding further test equipment) e.g. after the semi-conductor components have been installed in corresponding semi-conductor-component housings, and/or e.g. after the semi-conductor component housings (together with the semi-conductor components installed in them) have been installed in corresponding electronic modules (so-called “module tests”).
During the testing of semi-conductor components (e.g. during the above disk tests, module tests, etc.), so-called “DC tests” and/or e.g. so-called “AC tests” may in each case be applied as test procedures.
During a DC test for instance a voltage (or current) at a specific—in particular a constant—level may be applied to a corresponding connection of a semi-conductor component to be tested, whereafter the level of the—resulting—currents (and/or voltages) are measured—in particular tested to see whether these currents (and/or voltages) fall within predetermined required critical values.
During an AC test in contrast, voltages (or currents)—at varying levels—can for instance be applied to the corresponding connections of a semi-conductor component, particularly corresponding test sample signals, with the help of which appropriate function tests may be performed on the semi-conductor component in question.
With the aid of above test procedures defective semi-conductor components and/or modules may be identified and then removed (or else partially repaired as well as), and/or the process parameters—applied during the manufacture of the components in each case—may be appropriately modified and/or optimized, in accordance with the test results achieved, etc., etc.
In a plurality of applications—e.g. in server or workstation computers, etc., etc.—memory modules with data buffer components (so-called buffers) connected in series before them, e.g. so-called “buffered DIMMS”, may be used.
Memory modules of this nature generally contain one or several semi-conductor memory components, in particular DRAMs, as well as one or several data buffer components—connected in series before the semi-conductor memory components—(which may for instance be installed on the same printed circuit board as the DRAMs).
The memory modules are connected—in particular with a corresponding memory controller connected in series before them (for instance arranged externally to the memory module in question)—with one or several micro-processors of a particular server or work station computer, etc.
In “partially” buffered memory modules, the address and control signals—e.g. those emitted by the memory controller, or by the processor in question—may be (briefly) retained by corresponding data buffer components and then relayed—in chronologically co-ordinated, or where appropriate, in multiplexed or demultiplexed fashion—to the memory components, e.g. DRAMs.
In contrast, the (useful) data signals—emitted by the memory controller and/or by the respective processor—may be relayed directly—i.e. without being buffered by a corresponding data buffer component (buffer)—to the memory components (and—conversely—the (useful) data signals emitted by the memory components may be directly relayed to the memory controller and/or the respective processor).
In “fully buffered” memory modules in contrast, the address and control signals exchanged between the memory controller (and/or the respective processor), and the memory components, and also the corresponding (useful) data signals can first be buffered by corresponding data buffer components, and only then relayed to the memory components and/or the memory controller (or to the respective processor).
If the above memory module is subjected to an appropriate module test (for instance for testing the soldered joints and conductive tracks on the memory module, for instance the conductive tracks between the memory components/data buffer components) corresponding MBIST (MBIST=Memory Built In Self Test) devices can be provided on the data buffer components, and corresponding LFSR (LFSR=Linear Feedback Shift registers) devices.
In order to perform a corresponding module test, appropriate pseudo-random test (useful) data signals can be accordingly generated by the LFSR devices and relayed via corresponding data lines to the memory components, so that corresponding quasi-random test (useful) data is stored in the memory components.
The (test) address and (test) control signals required in order to perform the corresponding module tests can be generated by the above MBIST devices and relayed via corresponding address and control lines to the memory components.
The above procedure (in particular the use of pseudo-random test data signals generated by the LFSR devices) has the effect that—in contrast to the (test) address and (test) control signals present on the address and control lines—a relatively large number of differing frequency segments occurs in the test (useful) data signals present on the data lines, and/or that the test (useful) data signals consist of a relatively broad band of mixed frequencies.